Marius Hobbhahn, Lennart Heim, and Gökçe Aydos. Trends in machine learning hardware. 2023. URL:


Hans Aschauer, Gökçe Aydos, Markus Heintel, and Johannes Zwanzger. Method for operating keystream generators for secure data transmission. 2019. URL:


Markus Heintel, Hans Aschauer, Gökçe Aydos, Rainer Falk, Kai Fischer, Steffen Fries, Wolfgang Klasen, Axel Pfau, and Johannes Zwanzger. Method and device for transmitting a data set from a first to a second device. 2018. URL:


Gökçe Aydos. Parity-based Error Detection with Recomputation for Fault-tolerant Spaceborne Computing. PhD thesis, University of Bremen, Germany, 2017. URL:


Gökçe Aydos and Görschwin Fey. Empirical results on parity-based soft error detection with software-based retry. Microprocessors and Microsystems (MICPRO), September 2016. URL:, doi:10/bsmn.


Gökçe Aydos and Görschwin Fey. Exploiting error detection latency for parity-based soft error detection. In Design and Diagnostics of Electronic Circuits and Systems (DDECS). IEEE, April 2016. URL:, doi:10/bsf9.

[7] (1,2)

Gökçe Aydos and Görschwin Fey. Empirical results on parity-based soft error detection with software-based retry. In Nordic Circuits and Systems Conference (NORCAS). IEEE, October 2015. URL:, doi:10/bsmp.


Gökçe Aydos and Görschwin Fey. Parity-based soft error detection with software-based retry vs. triplication-based soft error correction - an analytical comparison on a flash-based FPGA architecture. In INFORMATIK 2015. GI e.V., September 2015. URL:


Gökçe Aydos and Görschwin Fey. In-circuit error detection with software-based error correction – an alternative to TMR. In Formal Modeling and Verification of Cyber-Physical Systems. Springer, 2015. URL:, doi:10/jqq2.


Carl Johann Treudler, Jan-Carsten Schröder, Fabian Greif, Kai Stohlmann, Gökçe Aydos, and Görschwin Fey. Scalability of a base level design for an on-board-computer for scientific missions. In Data Systems In Aerospace (DASIA). August 2014. URL:


Gökçe Aydos. FPGA-based coincidence-unit for digital positron emission tomography. Master's thesis, RWTH Aachen, 2012. URL:

Details about my work on error detection-based fault tolerance#

Here you find a summary of research publications on error detection-based fault-tolerance (EDFT) for sequential circuits like processors:

  • The idea came up when I was working on the satellite computer described in [10] which was part of the Eu:CROPIS satellite mission.

  • [9] introduces the idea of EDFT in general.

  • [8] gives a first insight to the performance of EDFT using parity-based error detection by comparing our approach with LTMR analytically. Synthesis results using a real circuit is gathered in [7].

  • [6] tries to improve the timing of EDFT using pipelining.

  • [5] is an extended version of [7] and provides a more detailed specification and fault tolerance analysis of transaction-based processing.

Finally [4] compiles my research work. Dissertation slides includes key diagrams and results of my dissertation.