Student Projects#
You find here currently available projects. The workload can be adjusted to fit the requirements of a thesis or semester project.
Parity-based error detection for digital circuits using Yosys#
FPGA reliability open source
Local triple modular redundancy (LTMR) is often the first choice to harden the flip-flops of an application against radiation-induced bitflips in space, but LTMR leads to an area overhead of roughly 300%. To cope with this significant overhead, an error detection based approach can be used [1]. To compare parity-based error detection with LTMR a tool for automatic application of these two approaches is needed.
Yosys is an open source synthesizer for digital logic. There is already a tool for applying LTMR based on Yosys [2].
Work packages#
Implementation of parity-based error detection using Yosys
Comparing the two approaches on a basic circuit regarding (1) maximum frequency, (2) area overhead and (3) processing time.
(stretch) Application and comparison on the RISC-V architecture.
Characterization of an HBM2-based FPGA accelerator#
FPGA parallel computing high bandwidth memory
Like GPUs, FPGA-based accelerators are used to improve processed data per Watt in data centers. Typically memory infrastructure on an FPGA is limited. To overcome this limit, high bandwidth memory (HBM) based FPGA accelerators emerged to increase the data throughput to the FPGA.
Work packages#
Literature research about (1) HBM memory based applications
Analysis of the AMD Xilinx Alveo U280 accelerator architecture to find out for which applications the HBM-based architecture is energy-efficient (characterization)
Implementation of an example application and comparison with its CPU-based counterpart.