Student Projects#

You find here currently available and past student projects.

Available#

Most of the projects are designed to be done as a masters thesis but the workload and work can still be adjusted to fit the requirements of a bachelors thesis or simple project work.

Parity-based error detection for digital circuits using Yosys#

FPGA reliability open source

Local triple modular redundancy (LTMR) is often the first choice to harden the flip-flops of an application against radiation-induced bitflips in space, but LTMR leads to an area overhead of roughly 300%. To cope with this significant overhead, an error detection based approach can be used 1. To compare parity-based error detection with LTMR a tool for automatic application of these two approaches is needed.

Yosys is an open source synthesizer for digital logic. There is already a tool for applying LTMR based on Yosys 2.

Work packages#

  • Implementation of parity-based error detection using Yosys

  • Comparing the two approaches on a basic circuit regarding (1) maximum frequency, (2) area overhead and (3) processing time.

  • (stretch) Application and comparison on the RISC-V architecture.

Characterization of an HBM2-based FPGA accelerator#

FPGA parallel computing high bandwidth memory

Like GPUs, FPGA-based accelerators are used to improve processed data per Watt in data centers. Typically memory infrastructure on an FPGA is limited. To overcome this limit, high bandwidth memory (HBM) based FPGA accelerators emerged to increase the data throughput to the FPGA.

Work packages#

  • Literature research about (1) HBM memory based applications

  • Analysis of the AMD Xilinx Alveo U280 accelerator architecture to find out for which applications the HBM-based architecture is energy-efficient (characterization)

  • Implementation of an example application and comparison with its CPU-based counterpart.

Spectrometry based on LEDs#

TODO

Comparison of Burrows Wheeler transformation on various computer architectures#

FPGA algorithms heterogeneous computing

Sequencing is the process of decoding gene information for medical diagnostics and biomedical research. Recent massive parallel sequencing3 techniques dramatically decreased the time and the costs involved in sequencing in last years, and paved the way for unprecedented medical diagnostics and prevention, e.g., for cancer patients.

Efficient computing of the work steps in the sequencing pipeline is beneficial to get results in a short time and in an energy-efficient way.

Sequence alignment is one of the steps in a sequencing pipeline. One of the popular algorithms used in sequence alignment is the Burrows–Wheeler transform (BWT).

In this project we want to compare BWT on different computing architectures. Some examples are:

  • Single-core processor

  • Multi-core processor

  • Two Multi-core processors connected on a mainboard

  • With GPU acceleration (e.g., Nvidia Tesla M60)

  • with FPGA acceleration on Alveo U280

Work packages#

  • literature research

    • available BWT software

    • computing platforms and results

  • preparation of BWT input datasets

  • implementation of BWT on Alveo U280

  • experiments

  • evaluation of

    • performance per Watt

    • runtime

    • quality of results

  • (stretch) heterogeneous computing: integration of the FPGA-based implementation in existing sequencing software

Past#

2021#

Master Theses#

  • Acceleration of Gaussian Elimination Algorithm on an FPGA, Amir Poorsadeg Zadeh Yeganeh

  • Investigating 2D SLAM algorithms in CPU-only Computing and GPU-accelerated Computing, Mohammed Aws, at BEC GmbH

  • Evaluation of state-of-the-art 3D feature descriptors for graph-based SLAM with LiDAR sensors, Hamit Zor, at Blickfeld GmbH

  • Development and Evaluation of a Computer Program for Clinical Assessment of Gene Mutation Data, Johanna Fenzl, at Deggendorf Institute of Pathology and Molecular Pathology


1

Aydos, Parity-based Error Detection with Recomputation for Fault-tolerant Spaceborne Computing

2

te Slaa, Fault tolerant techniques for finite state machines in hardware designs

3

Also called next generation sequencing (NGS)