# Publications

[ORCID](https://orcid.org/0000-0002-4183-9086), [Google Scholar](https://scholar.google.com/citations?user=NHyH7gEAAAAJ)

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## Details about my work on error detection-based fault tolerance

Here you find a summary of research publications on error detection-based fault-tolerance (EDFT) for sequential circuits like processors:

- The idea came up when I was working on the satellite computer described in {cite}`treudler2014scalability` which was part of the [Eu:CROPIS satellite mission](https://www.eoportal.org/satellite-missions/eu-cropis#searching-for-greenhouse-solutions).
- {cite}`aydos2015err_det_based_ft_intro` introduces the idea of EDFT in general.
- {cite}`aydos2015ltmr_vs_pbed_analy` gives a first insight to the performance of EDFT using parity-based error detection by comparing our approach with LTMR analytically. Synthesis results using a real circuit is gathered in {cite}`aydos2015ltmr_vs_pbed_exper`.
- {cite}`aydos2016exploiting_err_det_latency` tries to improve the timing of EDFT using pipelining.
- {cite}`aydos2016ltmr_vs_pbed_exper_extended` is an extended version of {cite}`aydos2015ltmr_vs_pbed_exper` and provides a more detailed specification and fault tolerance analysis of transaction-based processing.

Finally {cite}`aydos2017` compiles my research work. [Dissertation slides](https://f.aydos.de/dissertation-presentation.pdf) includes key diagrams and results of my dissertation.