Simulation using Verilator + GtkWave#
We typically start a language by saying hello world. Let us do that!
module m; initial begin $display("hello world"); end endmodule
I recommend running this using Verilator which is a popular open source Systemverilog simulator. Other popular simulators included in the development environments Vivado and Quartus are fine too, but I find simulating basic circuits using Verilator much easier and less time consuming.
Install Verilator and then compile & run it:
verilator --binary -j 0 m.sv obj_dir/Vm
Verilator converts the Systemverilog code into a simulator model in C++, so it can take some time to compile & run it. You should see the following message:
The program will continuously run in Verilator. You have to interrupt the program using CTRL+C. To stop the program automatically, add a
$finish; after the
Verification using simulation#
Typical circuits must be tested, because we often make errors during implementation, e.g., by misunderstanding the project specifications or simply by writing wrong code. Verification is the process of checking if an implementation behaves according to the functional specification.
Here we will implement a basic circuit and verify it according to the specification.
Example circuit: saturating arithmetic#
Let us describe a circuit which does byte addition but does not overflow. This is called saturation arithmetic.
Analyzing the waveform of circuits can ease the verification of circuits. Verilator is only for executing the model of the circuit. We need a waveform analyzer to see the waveform. The simulators included in popular integrated FPGA development tools integrate a waveform viewer.
After installing GtkWave clone verilator-minimal-example and make it:
git clone https://mygit.th-deg.de/gaydos/verilator-minimal-example cd verilator-minimal-example make make vis&
TODO how to add signals etc