# Structural Verilog for Combinational Circuits#

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## Learning Goals#

• Know how to create hierarchical designs using structural Verilog

• Know how to use and instantiate components in higher-level designs

## Background#

Exercise 101

Imagine that you want to implement a digital circuit which displays the decimal numbers 1 and 2 in loop on a seven segment display. How can you achieve this behavior?

Solution to Exercise 101

To create such a sequential behavior sequential logic can be used. There are two ways to implement sequential logic:

Most of the digital designs nowadays use synchronous sequential circuits. The reasons are depicted on the links above.

Exercise 102

What is a clock signal in a synchronous sequential circuit used for?

Solution to Exercise 102

A clock signal is a recurring signal typically swinging between logic high and low at a frequency. Clock signal is used to synchronize the components of a digital circuit.

Exercise 103

• What is a counter?

• How can we use a counter to create a slower clock?

Solution to Exercise 103

• In a synchronous design, a counter is input with a clock signal and typically outputs a sequence of values, e.g., from 0 to 1, from 1 to 2, etc.

Note that a counter does not necessarily output incrementing numbers. For example: LFSR.

• An incremental binary number counter with sufficient digits can be used to create slower clocks. For example the least significant digit of a counter will toggle with the half of the input frequency and 16th digit of a counter will toggle every $$2^{16}$$ cycles.

Multiplexers, binary decoders and seven-segment displays were already discussed in previous chapters.