A simple ALU

Source

Exercise 154

What is an arithmetic logic unit?

Solution to Exercise 154

It is a circuit which can carry arithmetic and logical operations like:

• addition

• comparison

• bitwise shift.

ALU is used in CPUs.

Learning Goals

• Understand how ALUs function

• Be able to describe a simple ALU in Verilog

Background

Arithmetic Logic Unit (ALU)

Source

Exercise 155

An ALU is controlled by some control signals.

1. How are these control signals called?

2. What do these control signals consist of?

3. Where do these control signals come from?

Solution to Exercise 155

1. opcode

2. An opcode consists of an operation and operand/s, e.g., compare a with b.

3. Opcodes are embedded in a compiled program as binary. They can also be recognized in assembly as mnemonics.

Exercise 156

Imagine you have an 8 bit ALU with following operations:

Opcode	Operation
0	No operation
1	Add
2	Subtract
3	Increment
4	Bitwise Inverse
5	Bitwise XOR
6	Bitwise OR
7	Bitwise AND

1. Design the bit slice circuits for this ALU.

2. How would the behavioral design for the operations look like?

Solution to Exercise 156

1. Structural bit slice design

We already designed addition and subtraction bit slices in previous chapters.

The bit slice has the inputs:

• input operands: a, b

• carry input: ci

and the outputs:

• result: r

• carry output: co

The following table shows the equations for the bit slice:

Opcode	Operation	Bitslice, f(a, b, ci) = r, co	Remarks
0	No operation	r = 0, co = 0
1	Add	r = a^b^ci, co = (a&b)|(a&ci)|(b&ci)	for carry, two signals active
2	Subtract	r = a^b^ci, co = (~a^b)|(~a&ci)|(b&ci)	similar to addition, but ~a
3	Increment	r = a~^ci, co = a|(a&ci)|ci	addition with b=1
4	Bitwise Inverse	r = ~a, co = 0
5	Bitwise XOR	r = a ^ b, co = 0
6	Bitwise OR	r = a | b, co = 0
7	Bitwise AND	r = a & b, co = 0

Additionally we have to include a multiplexer which selects the corresponding operation depending on the 3 bit opcode.

2. Behavioral design

In behavioral design we leave the implementation to the synthesizer. We only have to describe these operations using Verilog syntax. This has the advantage that we can conveniently describe the function for the whole byte without paying attention to the carry bits.

Opcode	Operation	Result byte
0	No operation	r = 0
1	Add	r = a + b
2	Subtract	r = a - b
3	Increment	r = a + 1
4	Bitwise Inverse	r = ~a
5	Bitwise XOR	r = a ^ b
6	Bitwise OR	r = a | b
7	Bitwise AND	r = a & b

Requirements

TODO