# SystemVerilog guide#

SystemVerilog guide by Zachary Yedida includes a compact introduction to the well-known language features of SystemVerilog. In this section we discuss the chapters including chapter 7.

## Introduction#

Exercise 184

What is the typical difference of SystemVerilog to traditional programming languages?

## A brief history#

Exercise 185

What is the difference between Verilog and SystemVerilog?

## Gate-level combinational modeling#

Exercise 186

What is the basic structure of a module?

### Modules#

#### The logic data type#

Exercise 187

logic data type is 4-state. What does this mean?

Exercise 188

1. What do the values X and Z mean?

Exercise 189

Why should we not use int to model signals?

Exercise 190

1. What is the difference between wire and var (variable)?

Exercise 191

Is logic a wire or var?

Exercise 192

Why is it sufficient to use the data type logic in FPGA design?

#### Module instantiation#

Exercise 193

In the example we see that and, or and not are instantiated even they were not defined before. How is this possible?

Exercise 194

How can we connect the ports of a module during instantiation? Show some of them and explain how they work.

#### Vectors#

Exercise 195

1. Model a 1-bit 4-to-1 multiplexer using the 1-bit 2-to-1 multiplexer mux with inputs a, b, sel and output f.

### Literals#

Exercise 196

How can we write integer literals?

Exercise 197

What happens if we assign a variable as follows: x = '1?

### Parameters#

Exercise 198

What is the difference between param and localparam?

## RT-level combinational modeling#

### Continuous assignments#

#### Conditional operator#

Exercise 199

How can we describe a 2-to-1 mux using a continuous assignment?

#### Bitwise operators#

Exercise 200

How can we shorten the following code?

assign
x = ~y,
x = ~y,
x = ~y;


#### Logical operators#

Exercise 201

Write code for the following as continuous assignment: x must be assigned 2 if the conditions a and b are true, and 3 otherwise.

#### Reduction operators#

Exercise 202

You have five two-way switches placed on different walls of your room that can control your room light. Every switch can toggle the light. Write code using a reduction operator that models this behavior. The switches are modeled by the signal logic [4:0] switches and the light as logic light.

#### Shift operators#

Exercise 203

What is the difference between a logical and arithmetic shift?

#### Concatenate and replicate operators#

Exercise 204

You have the signals a, b, c. Create the concatenation of signals aabcabcabcb and assign to f.

### Always block for combinational design#

Exercise 205

What is the advantage of using an always_comb statement over a simple always or a continuous assignment?

#### Blocking assignment#

Exercise 206

Why should we use blocking assignments for combinational circuit design and non-blocking assignments for sequential circuits?

#### Case statements#

Exercise 207

When does the compiler infer a mux from a case statement?

#### Unique case#

Exercise 208

What is the difference between case and unique case?

## Modeling sequential circuits#

### Always block#

Exercise 209

Why should we typically use always with a sensitivity list (e.g., @(posedge clk) or always_comb)?

#### Non-blocking assignments#

Exercise 210

We say: a non-blocking assignment is deferred and executed later. (1) When is it executed? (2) What happens if we have a later assignment to the same destination variable?

### The D flip-flop and register#

Exercise 211

You are describing a flip-flop. Is there a difference between q <= d and q = d in the template below? In other words, would it behave differently?

module m (input clk, d, output logic q);
always_ff @(posedge clk)
q <= d;  // or q = d
endmodule


#### More on blocking vs non-blocking#

Exercise 212

Imagine you want to implement a 3 bit register that shifts a bit at every cycle. What is the problem with the following code?

always_ff @(posedge clk) q0 = d;
always_ff @(posedge clk) q1 = q0;
always_ff @(posedge clk) q2 = q1;
assign d = q2;


### The D latch#

Exercise 213

You want to implement a multiplexer. (1) Do you see a problem with the following code? (2) What does the compiler synthesize out of this code?

module m (input [1:0] sel, input a, b, c, output logic y);
always_comb
case (sel)
'b01: y = a;
'b10: y = b;
'b11: y = c;
endcase
endmodule


### General sequential circuit design#

Exercise 214

Draw the structure of typical sequential circuits. Use state register, next-state logic and output logic.

## Modeling finite state machines#

Exercise 215

What is the difference between a Mealy and Moore machine?

### State diagrams#

Exercise 216

What is the difference in Mealy and Moore state machine diagrams?

Exercise 217

What are some differences between Mealy and Moore state machine circuit behaviors?

### Enumerations#

Exercise 218

How can we use enumerations in state machine design?

### FSM code development#

Additional info in State machine example

## Modeling memory#

### Register file#

Exercise 219

How can we model a register file which consists of 32x 64bit registers?

### RAM#

Exercise 220

How can we model a RAM?

### Dual-port RAM#

Exercise 221

Where are dual-port RAMs useful?

Where do we have to place \$readmemh() to initialize a memory array?